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| CXD2434ATQ Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2434ATQ is an IC developed to generate the timing pulses required by the Progressive Scan CCD image sensors as well as signal processing circuits. The CXD2434ATQ adds EFS operation when using the high-speed electronic shutter and other changes to the CXD2434TQ specifications. Features * External trigger function * Electronic shutter function * Supports non-interlaced operation * 30 frames/s * Built-in driver for the horizontal (H) clock * Base oscillation 1560 fH (24.5454 MHz) Applications Progressive Scan CCD cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX084AK, ICX084AL 48 pin TQFP (Plastic) Absolute Maximum Ratings (Ta=25 C) * Supply voltage VDD VSS -0.5 to +7.0 * Input voltage VI VSS -0.5 to VDD +0.5 * Output voltage VO VSS -0.5 to VDD +0.5 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -55 to +150 Recommended Operating Conditions * Supply voltage VDD 4.75 to 5.25 * Operating temperature Topr -20 to +75 V V V C C V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. --1-- E97841-TE CXD2434ATQ XCPDM XCPOB Block Diagram BUSY PBLK WEN ID STDBY SMDE 26 36 35 34 33 32 31 47 46 42 29 WM HD 25 FSE VD RG 10 H1 13 H2 14 XSHP 21 XSHD 22 XRS 23 XV1 18 XV2 17 XV3 16 XSG 19 CLD 39 CL 38 CKO 40 1/2 GATE COUNTER PULSE GENERATOR DECODE TG REGISTER 3 PS 4 5 7 8 9 STRB DCLK DATA SMD1 SMD2 11 XSUB 28 TEST1 48 TEST2 41 RESET 1 OSCO 2 OSCI 43 44 45 6 VSS 12 15 20 24 27 30 37 ESG EFS SCPDM XCPOB TEST1 Pin Configuration (Top View) BUSY PBLK WEN ID TRIG VDD VDD SMDE WM VDD 36 VSS 37 CL 38 CLD 39 CKO 40 RESET 41 STDBY 42 35 34 33 32 31 30 29 28 27 26 25 24 VSS 23 XRS 22 XSHD 21 XSHP 20 VDD 19 XSG CXD2434ATQ TRIG 43 ESG 44 EFS 45 HD 46 VD 47 TEST2 48 18 XV1 17 XV2 16 XV3 15 VSS 14 H2 13 H1 1 OSCO 2 OSCI 3 PS 4 STRB 5 DCLK 6 VSS 7 DATA 8 SMD1 9 SMD2 10 11 12 RG XSUB --2-- VDD FSE VSS VDD VSS VSS VSS VSS CXD2434ATQ Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Symbol OSCO OSCI PS STRB DCLK VSS DATA SMD1 SMD2 RG XSUB VDD H1 H2 VSS XV3 XV2 XV1 XSG VDD XSHP XSHD XRS VSS FSE SMDE VSS TEST1 WM VDD XCPDM XCPOB PBLK ID WEN BUSY VSS CL CLD I/O O I I I I -- I I I O O -- O O -- O O O O -- O O O -- I I -- I I -- O O O O O O -- O O Description Inverter output for oscillation. Inverter input for oscillation. Switching for electronic shutter speed input method. (With pull-up resistor) Low: Serial input, High: Parallel input Shutter speed setting. (With pull-up resistor) Shutter speed setting. (With pull-up resistor) GND Shutter speed setting. (With pull-up resistor) Shutter mode setting. (With pull-up resistor) Shutter mode setting. (With pull-up resistor) Reset gate pulse output. CCD discharge pulse output. Power supply. Clock output for horizontal CCD drive. Clock output for horizontal CCD drive. GND Clock output for vertical CCD drive. Clock output for vertical CCD drive. Clock output for vertical CCD drive. Sensor charge readout pulse output. Power supply. Sample-and-hold pulse output. Sample-and-hold pulse output. Sample-and-hold pulse output. GND Switching for external trigger discharge operation. (With pull-up resistor) Low: No high-speed discharge, High: High-speed discharge Switching for readout timing. (With pull-up resistor) Low: ESG input valid, High: ESG input invalid GND Test. (With pull-down resistor) WEN mode setting. (With pull-down resistor) Low: Effective line, High: XSG synchronization Power supply. Clamp pulse output. Clamp pulse output. Blanking cleaning pulse output. Line identification output. Write enable output. Trigger mode flag output. GND 780 fH clock output. AD conversion pulse output. --3-- CXD2434ATQ Pin No. 40 41 42 43 44 45 46 47 48 Symbol CKO RESET STDBY TRIG ESG EFS HD VD TEST2 I/O O I I I I I I I I 1560 fH clock output. Description RESET. (With pull-up resistor) Low : Reset, High : Normal Standby. (With pull-up resistor) Low: Internal clock supply stopped, High: Normal External trigger input. (With pull-up resistor) External readout input. (With pull-up resistor) Vertical CCD discharge input. (With pull-up resistor) Horizontal sync signal input. Vertical sync signal input. Test. (With pull-up resistor) Electrical Characteristics 1. DC Characteristics Symbol Supply voltage VDD Input voltage 1 VIH1 (Input pins other than those listed below) VIL1 Input voltage 2 VIH2 (Pin 2) VIL2 Output voltage 1 VOH1 (Output pins other than those listed below) VOL1 Output voltage 2 VOH2 (Pins 21, 22, 23, 38, 39 and 40) VOL2 Output voltage 3 VOH3 (Pin 10) VOL3 Output voltage 4 VOH4 (Pins 13 and 14) VOL4 Output voltage 5 VOH5 (Pin 1) VOL5 Feedback resistor RFB Pull-up resistor RPU Pull-down resistor RPD Current consumption IDD Item Conditions VDD=4.75 V to 5.25 V Topr= -20 to +75 C Min. 4.75 0.7 VDD 0.7 VDD 0.3 VDD IOH=-2.5 mA IOL=4.5 mA IOH=-5.0 mA IOL=9.0 mA IOH=-7.5 mA IOL=13.5 mA IOH=-14.0 mA IOL=24.0 mA VDD-0.4 0.4 VDD-0.4 0.4 VDD-0.4 0.4 VDD-0.4 0.4 VDD/2 VDD/2 VIN=VSS or VDD VIL=0 V VIH=VDD VDD=5 V 1M 50 k 50 k 40 100 k 100 k Typ. 5.0 Max. 5.25 0.3 VDD Unit V V V V V V V V V V V V V V V mA --4-- CXD2434ATQ 2. AC Characteristics 1) Waveform characteristics of H1, H2 and RG 0.9VDD H1 0.1VDD tRH1 tWH1 tFH1 0.9VDD H2 0.1VDD tFH2 tWH2 tRH2 0.9VDD RG 0.1VDD tRRG tWRG tFRG VDD=5.0 V, Topr=25 C, load capacitance of H1 and H2=100 pF, load capacitance of RG=10 pF Symbol tRH1 tFH1 tWH1 tRH2 tFH2 tWH2 tRRG tFRG tWRG Definition H1 rise time H1 fall time H1 high level time H2 rise time H2 fall time H2 low level time RG rise time RG fall time RG high level time Min. Typ. 6 5 35 6 5 35 2 2 15 Max. 15 15 15 15 5 5 20 Unit ns ns ns ns ns ns ns ns ns 25 25 10 --5-- CXD2434ATQ 2) Phase characteristics of H1, H2, RG, XSHP, XSHD, XRS, CL, CLD and CKO tH1 H1 0.5VDD 0.5VDD 0.5VDD H2 tPD3 RG 0.5VDD tPD4 tW1 XSHP 0.5VDD 0.5VDD 0.5VDD tPD1 tPD2 0.5VDD tPD5 0.5VDD tW2 tPD6 XSHD 0.5VDD tPD7 0.5VDD XRS 0.5VDD tPD8 0.5VDD tPD10 tW4 tW3 tPD9 0.5VDD CLD 0.5VDD CL 0.5VDD 0.5VDD tW5 CLO 0.5VDD tPD11 0.5VDD 0.5VDD tW5 0.5VDD tPD11 VDD=5.0 V, Topr=25 C, load capacitance of CL and CKO=30 pF, load capacitance of CLD, XSHP, XSHD, XRS and RG=10 pF Symbol tH1 tPD1 tPD2 tPD3 tPD4 tPD5 tPD6 tPD7 tPD8 tPD9 tPD10 tPD11 tW1 tW2 tW3 tW4 tW5 Definition H1 cycle H2 rising delay, activated by the falling edge of H1 H2 falling delay, activated by the rising edge of H1 H1 rising delay, activated by the rising edge of RG XSHP falling delay, activated by the falling edge of RG H1 falling delay, activated by the rising edge of XSHP H1 rising delay, activated by the rising edge of XSHD CLD falling delay, activated by the falling edge of XSHD CLD falling delay, activated by the rising edge of XRS XRS falling delay, activated by the falling edge of CLD CL falling delay, activated by the rising edge of H1 H1 rising (falling) delay, activated by the rising edge of CKO XSHP pulse width XSHD pulse width CLD pulse width CL pulse width CKO pulse width --6-- Min. -5 -5 -5 -2 -7 -5 -5 17 0 -5 -5 13 15 17 38 17 Typ. 82 0 0 0 4 2 2 2 22 8 0 2 18 20 22 41 20 Max. 5 5 5 10 7 7 7 27 15 5 7 23 25 27 45 24 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CXD2434ATQ 3) Phase conditions of HD, VD, TRIG, EFS and ESG CL 0.5VDD tSETUP tHOLD HD, VD, TRIG EFS, ESG 0.5VDD 0.5VDD VDD=5.0 V, Topr=25 C, load capacitance of CL=30 pF Symbol tSETUP tHOLD Definition HD, VD, TRIG, EFS and ESG setup time, activated by CL HD, VD, TRIG, EFS and ESG hold time, activated by CL Min. 20 5 Typ. Max. Unit ns ns 4) Phase characteristics of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID CL 0.5VDD 0.5VDD tPDCL1 XV1, XV2, XV3 0.5VDD tPDCL2 BUSY, WEN, ID 0.5VDD tPDCL3 XSG, PBLK, XCPDM, XCPOB 0.5VDD VDD=5.0 V, Topr=25 C, load capacitance of CL=30 pF, load capacitance of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID=10 pF Symbol Definition tPDCL1 XV1, XV2 and XV3 delay, activated by the falling edge of CL tPDCL2 BUSY, WEN and ID delay, activated by the rising edge of CL XSG, PBLK, XCPDM and XCPOB delay, activated by the tPDCL3 rising edge of CL Min. 30 40 40 Typ. Max. 65 60 55 Unit ns ns ns --7-- CXD2434ATQ Description of Functions 1. Progressive Scan CCD drive pulse generation * Combining this IC with a crystal oscillator generates a fundamental frequency of 24.5454 MHz. * CCD drive pulse generation is synchronized with the HD and VD inputs. Set fCL to 780 fHD and fHD to 525 fVD. * The various operations are performed by the TRIG, EFS and ESG inputs. (See the following items.) CL 1 HD 35 H1 T1 Detection timing for VD, TRIG, EFS and ESG After HD input is detected, the status of VD, TRIG, ESG and EFS is detected during T1. Do not change the status of VD, TRIG, ESG and EFS during T1. When input is from a non-synchronized system, the low level period for each pulse should be set to 63.5 s or longer to prevent misoperation. 2. Reset The internal register values are undetermined immediately after power-on, so perform one of the following reset operations. 1. Reset by the RESET pin Reset is performed by setting the RESET pin low for a period of 80 ns or more. Reset can also be performed by setting the RESET pin low during power-on and then switching the RESET pin from low to high when VDD rises to 4.75 V or higher. Note that when reset is performed by the RESET pin, the electronic shutter settings made by serial input are also reset. 2. Reset by turning off the electronic shutter Reset is performed by setting the shutter mode to electronic shutter off and inputting VD. Note that in this case the TRIG, ESG and EFS pins should all be set high. --8-- CXD2434ATQ 3. Electronic shutter STRB DCLK DATA SMD2 SMD1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SMD1 H L H SMD2 H H L Mode Electronic shutter off (1/30 s accumulation) High-speed electronic shutter Low-speed electronic shutter D0 to 9 -- Number of exposed lines (Note 1) Number of exposed frames (Note 2) Note 1) Relationship between the number of exposed lines and the exposure time The relationship between the number of exposed lines and the exposure time is as follows. (Exposure time)=(Number of exposed lines) x (One horizontal scan period) + (Accumulation time for the readout lines) In this formula, one horizontal scan period equals the HD falling interval, and the accumulation time for the readout lines is the time from the rising edge of XSUB to the rising edge of XSG (456 bits). Also, (Number of exposed lines) should be set to greater than 1 but less than 524. Note 2) The number of exposed frames should be set to greater than 1 but less than 1023. However, when the number of exposed frames is 1 and SMDE is set to high, external trigger mode does not function. Timing Chart (Serial input) STRB tWD DCLK tSDD DATA tHDD tSDS tWS --9-- CXD2434ATQ AC characteristics for serial input Symbol tSDD tHDD tSDS tWS tWD Definition DATA setup time, activated by the rising edge of DCLK DATA hold time, activated by the rising edge of DCLK DCLK setup time, activated by the falling edge of STRB STRB pulse width DCLK pulse width Min. 10 ns 10 ns 10 ns 82 ns 82 ns Max. -- -- -- -- -- 3-2. [Parallel input] Mode Electronic shutter off Flickerless PS H H H H H H H H H H H H H H H H H H SMD1 H L L L L L L L L L H H H H H H H H SMD2 H L H H H H H H H H L L L L L L L L STRB X X H L H L H L H L H L H L H L H L DCLK X X H H L L H H L L H H L L H H L L DATA X X H H H H L L L L H H H H L L L L Exposure time 1/30 s 1/50 s 1/60 s 1/125 s 1/250 s 1/500 s 1/1000 s 1/2000 s 1/4000 s 1/10000 s 2 FRM 3 FRM 4 FRM 5 FRM 6 FRM 7 FRM 8 FRM 9 FRM High-speed shutter Low-speed shutter --10-- CXD2434ATQ 4. External trigger mode External trigger mode starts exposure in sync with the external trigger input. No special pins are required to set this mode. The IC prepares to shift to external trigger mode with the falling edge of the TRIG pin (Note). The timing to shift to external trigger mode varies according to the mode setting. (See the table.) The BUSY pin maintains high status during external trigger mode. Whether or not to discharge the vertical CCD charge is set by FSE. Note) See the detection timing for VD, TRIG, EFS and ESG. Mode settings during external trigger (Note 1) PS L H H X X SMD1 SMD2 Description of operation L X The IC is shifted to external trigger mode by HD, exposure is finished after the set L H time, and XSG is output. (Note 2) (Note 3) The IC is shifted to external trigger mode by HD, exposure is finished 1/50 s later, L L and XSG is output. H L Do not set for external trigger. H H Trigger input is not accepted. Note 1) The SMD1 and SMD2 setting method varies according to the PS status. See "3. Electronic shutter". PS=Low : Set by serial input. PS=High : Set by the SMD1 and SMD2 pins. Note 2) The exposure time setting method is the same as the exposure time setting for the electronic shutter. Note 3) When FSE=high, set the number of exposed lines from 1 to 522. --11-- CXD2434ATQ 5. Discharge of the vertical CCD During EFS is low, discharge of the vertical CCD is performed. During FSE is high in the external trigger mode, the vertical control line by line is possible. That is different from discharge operation. The falling in the effective interval of EFS is detected, discharge is not performed even if the low status is held until the next effective period. For frames using EFS, set electronic shutter off or high-speed electronic shutter. When EFS is used, WEN (WM=low) may not indicate the proper status. n-1 EFS n n+1 XV1 XV3 Timing Chart 2 n CL n+1 XV3 CXD2434ATQ 7. Mode settings 7-1. VD input-related BUSY H SMD1 L H L X X SMD2 H L H X X SMDE X EFS X H L VD input Invalid Readout operation or the number of accumulated frames is counted. Readout operation is performed. Invalid Note 1) When PS is high, SMD1 and SMD2 indicate the status of the SMD1 and SMD2 pins, respectively. When PS is low, these are the corresponding internal register values. See "3. Electronic shutter". Note 2) Operation when PS=high, SMD1=low and SMD2=low conforms to that when SMD1=low and SMD2=high. 7-2. TRIG, ESG and EFS input-related BUSY Discharge period (Note 1) H Exposure period Signal output period Before TRIG input L After TRIG input (Note 2) (Note 3) IC shifted to external trigger mode (Note 3) Prohibited SMDE X H L Prohibited Readout operation (Note 4) Prohibited Discharge operation (Note 6) (Note 7) Prohibited (Note 5) Prohibited TRIG ESG Prohibited EFS Invalid X Note 1) Only when FSE is high. Note 2) Valid only during low-speed shutter. Note 3) See "4. External trigger mode". Note 4) ESG input is valid only one time after TRIG input. Do not input ESG two times or more. Note 5) Fix ESG to high status when BUSY is low. Note 6) When EFS is low, readout is not activated by VD input. See "7-1. VD input-related". Note 7) Use in electronic shutter off state. Note 8) In case any two pins or more among TRIG, ESG, and EFS are falled at the same time, the operation is not guaranteed. 7-3. WEN mode switching by WM WM L H Description of WEN operation Lines for which the signal from the CCD is valid output high; all other lines output low. Output is synchronized with XSG. --13-- Application Circuit +5V 36 24 23 22 21 20 19 CXD2434ATQ 18 17 16 15 14 13 CXA2006Q CXD2311AR 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 Reset Circuit 41 42 43 --14-- 3 4 5 6 9 10 11 12 44 45 46 47 48 1 2 7 8 +15V 100k 1000p CXD1267AN ICX084AK/AL CXD2434ATQ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Normal Operation (vertical synchronization) VD HD 1 14 OUT 123456781234 494 XV1 XV2 XV3 XSG --15-- XSUB PBLK XCPOB XCPDM ID WEN (WM=High) WEN (WM=Low) CXD2434ATQ BUSY 508 510 Normal Operation (horizontal synchronization) 780 HD 1 35 1 35 71 47 95 72 95 59 83 78 CL XV1 XV2 XV3 XSG (=High) XSUB H1 H2 --16-- 35 31 93 RG XSHP XSHD XRS PBLK 120 109 119 12 XCPOB XCPDM ID WEN BUSY CXD2434ATQ XSUB may be kept high depending on the electronic shutter setting. 107 Normal Operation: readout timing (horizontal synchronization) HD 35 107 83 78 CL 35 XV1 71 XV2 47 59 XV3 520 576 XSG 551 XSUB (=High) H1 H2 --17-- 31 93 RG XSHP XSHD XRS 780 1 1 PBLK (=Low) XCPOB 12 109 XCPDM 119 ID WEN (=Low) CXD2434ATQ BUSY =High(trig) Low(others) External Trigger Mode: high-speed electronic shutter, discharge (FSE=high, SMDE=high, SMD1=low, SMD2=high) TRIG VD HD 1 1 27 14 OUT 123456781234 RG XV1 XV2 XV3 --18-- XSG XSUB PBLK XCPOB XCPDM ID WEN (WM=High) WEN (WM=Low) CXD2434ATQ BUSY See "3. Electronic Shutter" for the time from TRIG input to XSG. The fall of VD is invalid during the period while BUSY=high. 508 External Trigger Mode: high-speed electronic shutter, when discharge starts (FSE=high, SMD1=low, SMD2=high) 1 2 3 TRIG 780 1 HD CL 35 77 56 42 70 72 95 49 63 XV1 XV2 XV3 XSG (=High) XSUB H1 --19-- 35 31 93 H2 RG XSHP XSHD XRS PBLK 12 XCPOB XCPDM ID WEN CXD2434ATQ BUSY 35 External Trigger Mode: high-speed electronic shutter, when discharge finishes (FSE=high, SMD1=low, SMD2=high) 499 500 HD CL XV1 XV2 XV3 XSG (=High) XSUB H1 --20-- H2 RG XSHP XSHD XRS PBLK =(Low) XCPOB (=High) XCPDM (=High) ID WEN (=Low) BUSY (=High) CXD2434ATQ External Trigger Mode: high-speed electronic shutter, no discharge (FSE=low, SMDE=high, SMD1=low, SMD2=X) TRIG VD HD 1 14 OUT 1 2 3 4 5 6 7 812 3 4 RG XV1 XV2 --21-- XV3 XSG XSUB PBLK XCPOB XCPDM ID WEN (WM=High) WEN (WM=Low) CXD2434ATQ BUSY See "3. Electronic Shutter" for the time from TRIG input to XSG. The fall of VD is invalid during the period while BUSY=high. 508 Example during ESG Input (FSE=high, SMDE=low, SMD1=low, SMD2=X) TRIG ESG VD HD 1 1 27 14 OUT 1 2 3 45 6 7 81 2 3 4 RG XV1 XV2 --22-- XV3 XSG XSUB PBLK XCPOB XCPDM ID WEN (WM=High) WEN (WM=Low) BUSY CXD2434ATQ The fall of VD is invalid during the period while BUSY=high. 508 Example during EFS Input (trigger mode: FSE=high, SMDE=high, SMD1=low, SMD2=X) TRIG EFS 42 bits x104 times VD HD 1 1 6 27 13 256 98 99 339 340 OUT RG XV1 XV2 --23-- XV3 XSG XSUB PBLK XCPOB XCPDM ID WEN (WM=High) WEN (WM=Low) BUSY CXD2434ATQ The fall of VD is invalid during the period while BUSY=high. 264 During EFS Input, when discharge starts EFS 780 1 CL 35 56 42 70 49 63 77 XV1 XV2 XV3 XSG (=High) XSUB (=High) H1 --24-- 35 31 93 H2 RG XSHP XSHD XRS PBLK 12 XCPOB XCPDM ID WEN CXD2434ATQ BUSY 35 107 HD During EFS Input, when discharge finishes EFS HD CL XV1 XV2 XV3 XSG (=High) XSUB H1 --25-- H2 RG XSHP XSHD XRS PBLK =(Low) XCPOB (=High) XCPDM (=High) ID WEN (=Low) BUSY (=Low) CXD2434ATQ CXD2434ATQ Package Outline Unit : mm 48PIN TQFP (PLASTIC) 9.0 0.4 7.0 0.2 36 25 1.27 MAX 1.0 0.1 0.1 37 24 A 48 13 1 0.5 12 0.2 0.1 0.08 M 0.125 0.05 0.1 0.1 + 7 3 - 3 DETAIL A 0.5 0.2 1.0 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE TQFP-48P-L071 TQFP048-P-0707-AN --26-- |
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